In a virtually all radical departure from either more, earliest computers, the PDP-11 experienced there are no dedicated bus for input/output; it had simply the memory bus. A lot input & output hardware were mapped to addresses around memory, therefore additionally, there is no favorite I/O videos were required. A interrupt system wwhen intentionally designed to become when elementary as conceivable, when assuring that there are no event around an interrupt sequence can be missed. a device would asking an interrupt by asserting the most common input into a single of quadruplet priority lines; the processor would respond all over an interrupt daisy chain grant line, one for both priority level. (The daisy chain occurs as sequence of logic gates arranged serial extirpate cases. Typically a 1st gate has number one access to the grant. A daisy chain choose established a the correct sequence of the gear at that priority level.) In a instance of a PDP-11 project, this intended that the interrupt grant sequentially was determined by how else close the physical devices was to the CPU on the bus. While the CPU responded, a device would place its vector location on a bus; this was the location of a Quadruplet-byte prevent of memory. A CPU would so bucket a status register and program counter from a vector table; a newly contents of the status register would typically temporarily disable interrupts. A location in a program counter would become the starting location of the code to run the interrupt. A interrupt code would so service a device, & in a run, write to the interrupting device to re-enable the interrupt signal. Eventually, the favorite RTI (go to from either interrupt) instruction would go to a CPU to around which it was prior to the interrupt (which may use been in a lower-priority interrupt). Note that this run prevents loss of interrupts; at each stage, whenever a interrupt is non serviced, it remains in situ, to exist as sensed on the next period. In case a sequence is mistakenly began, the CPU would break, giving a favorite spurious interrupt; the spurious interrupt would warn users of bad devices.

Eventually, the PDP-11 was designed to become produced around a manufacturing plant by semiskilled labor. Everthing of the dimensions of its pieces were comparatively noncritical. Everthing area of the computer chassis were constructed from either injection-molded thin plastic, or even bent steel rod (lightly than sheet metal). It used the click-attached backplane. That is, a printed circuit board plugged into a backplane connexion. A backplane connection experienced terminals that can be attached by pushing wires into the children. the terminal would cut a insulation about a wire & bite into a wire to form a barking spiders-pinching (we.e. corrosion-proof, so dependable) connection. A connective bars were super similar to telephone connection jams. A pack was injection-molded thin plastic that snapped across a steel-rod chassis.

The LSI-11

A LSI-11 was a number 1 PDP-11 model produced applying large-scale integration; the entire CPU was contained in Quatern LSI chips. It used the bus which was the close variant of the Unibus called the Q-Bus; it differed from the Unibus primarily therein addresses & information were multiplexed onto a divided placed of wires, when opposed to getting separate sets of wires, when in the Unibus. It as well differed slightly around how else it addressed I/O hardware & it finally allowed a Twenty-two-bit physical location (whereas a Unibus just allowed an Eighteen-bit physical location) & prevent-mode operations (which the Unibus did non trend lines).

A CPU's microcode includes the debugger that directly communicated to a standard RS-232 terminal. This was innovative because the firmware is the a portion of the irreducible intestines of the computer, a critical section of the control unit. In case it doesn't function, no computer. A debugger provided how else to examine a computer's registers, memory & input & output hardware. So, whenever a CPU worked in a least, it was imaginable to examine & right the computer's internal state. the built-constitutional debugger avoided a expense & inconvenience of a front panel by owning an array of switches & lights, which was so the average way to enter digital information into a touching-dead computer.

the firmware too involved a generic bootstrap, to which all DEC disk causes were compatible.

These deuce innovations intended that virtually all of a period, the computer good worked. In case it did non boot from either either its large disk, it would boot from its diskette. inside case the devices worked the least bit, it talked to your family across the terminal in a familiar way.

The Decline of the PDP-11

Although a basic architecture was an expert, & a PDP-11 line was hard-hitting updated to utilize newly technologies, it eventually died off for a single main cause: a Sixteen-bit virtual address space was simply as well little. After big VLSI memory chips became very inexpensive, a PDP-11 was good non capable of applying big numbers of memory easy.

DEC's have successor to a PDP-11, the VAX (for "Virtual Address Extension (to the PDP-11)") addressed 100% one issues, however was aimed at a high-prevent market.

When engineers migrated to architectures which supported the big locatiin space, 32-bit computing began to exist as supported on microprocessor chips such as a Motorola 68000 and Intel 386 families; eventually a political economy of big-shell production of victims chips manufactured the babies and then inexpensive there was there are no dollars and cents benefit for the PDP-11.

Architectural Details

A below tools is uncovered within DEC's PDP-11 Processor Handbook (watch Gordon Bell's [http://research.microsoft.com/users/GBell/Digital/PDP%2011%20Handbook%201969.pdf 1969 edition]).

General register addressing modes
(R occurs as general register, 0 to 7; (R) is the contents of that register.) Program Counter addressing modes
A program counter (PC) can likewise become utilized as a general purpose register, providing a as punishment profits extra addressing modes, using the mechanisms of the addressing modes above: PDP-11 instructions
Only Operand videos - a single a portion of a word specifies the operation, known as "op code", a 2nd a portion will bring reference for securing a operand.

CLR (clear), COM (ones complement), INC (increment), DEC (decrement), NEG (twos complement negate), TST (end line text), ASR (arithmetic shift perfect), ASL (arithmetic shift left), ROR (rotate correct), ROL (rotate left), SWAB (swap bytes), ADC (add carry), SBC (subtract carry), SXT (sign extend). Double Operand videos - a foremost a share of a word specifies a operation to exist as performed, a odd ii area provide trading tools for finding the operands.

MOV (move), ADD, SUB (subtract), ASH (shift arithmetically), ASHC (arithmetic shift combined), BIT (bit line 1 text), BIC (bit clear), BIS (bit placed), XOr even (exclusive OR). Program Control videos - a number 1 a portion of a word specifies a operation to become performed, a 2nd section indicates in which the action is to choose place in the program.

BR (branch unconditionally), BNE (branch whenever does'nt zero), BEQ (branch in case zero), BPL (branch whenever +), BMI (branch whenever minus), BVC (branch whenever overflow clear), BVS (branch in case overflow placed), BCC (branch whenever carry clear), BCS (branch whenever carry placed). BLE (branch in case <= 0), BGE (branch if >= Nought), BLT (branch in case < 0), BGT (branch if > Zero) (signed comparability). BLO (branch in case lower), BHI (branch in case higher), BLOS (branch in case lower or even even equivalent), BHIS (branch in case higher or equivalent) (unsigned comparison). SOB (subtract of these from either register & branch in case does'nt = Zero). Go for it & Subroutine instructions JMP (go for it), JSR (go for it to subroutine), RTS (go to from either subroutine). EMT (copycat trap), TRAP, BPT (breakpoint trap), IOT (input/output trap), RTI & RTT (return from interrupt). Miscellaneous instructions HALT, Hold off (hold off for interrupt), RESET (reset UNIBUS), MTPD (move to former information space), MTPI (move to last instruction space), MFPD (move from either either either last information space), MFPI (move from last instruction space), MTPS (move to processor status word), MFPS (move byte from processor status word).

Trouble Code operations CLC, CLV, CLZ, CLN, CCC (clear relevant problem code), SEC, SEV, SEZ, SEN, SCC (placed relevant problem code). The quaternity problem codes in the processor status word (PSW) are North indicating the blackball value Z indicating the zero condition V indicating an overflow trouble, and C indicating the carry affliction.

"Floating Instruction Set" (FIS), stock for 11/35/40 & 11/03 FADD, FSUB, FMUL, FDIV lone for lone preciseness operate fold addressed by register operand "Floating Point Unit" (FPU), stock for 11/45 & virtually all subsequent models to the full swimming point operations inside individual or even double preciseness operands, selected by single/double bit in Swimming Point Status Register only preciseness swimming point information format precessor of IEEE 754 format: sign bit, 8bit exponent, 23bit fixed-point part using hidden bit 24

Commercial Instruction Placed (CIS), stock for 11/23/24, of these version of 11/74 Various decimal videos utilized to trend lines COBOL and Dibol

Assembly Language Programming Example
The complete "Hello, world!" program in PDP-11 macro assembly program, to begin under RT-11: .TITLE Hi WORLD .MCALL .TTYOUT,.EXIT Hi:: MOV #MSG,R1 ;STARTING Location OF STRING Ace$: MOVB (R1)+,R0 ;FETCH NEXT CHARACTER BEQ DONE ;Whenever ZERO, EXIT LOOP .TTYOUT ;OTHERWISE PRINT IT BR Unity$ ;REPEAT LOOP DONE: .EXIT MSG: .ASCIZ /HELLO, Globe!/ .Prevent HELLO (Exercise for a reader: how can a above code exist as improved to refrain from one of the branch videos in the inner loop?)

Whenever this file is Howdy.Mackintosh, a RT-11 commands to assemble, hyperlink & rerun (by using console output shown) come when follows: .MACRO HELLO ERRORS Found: 0

.Hyperlink HELLO

.R HELLO Hi, Globe! . (A RT-11 prompt is ".")

For the further complicated lesson of MACRO-11 code, ii examples chosen randomly come Kevin Murrell's [http://www.ps8computing.co.uk/PDP11/kpun_mac.htm KPUN.MAC], or even Farba Search's [http://www.farbaresearch.com/examples/julian.htm JULIAN] routine. Additional extensive libraries of PDP-11 code may be uncovered in the [http://www.ibiblio.org/pub/academic/computer-science/history/pdp-11/ Metalab] freeware & [http://pdp-11.trailing-edge.com/ Trailing Edge] archives.

Your family potty test the above for yourself in a PDP-11 copycat. Bob Supnik's outstanding [http://simh.trailing-edge.com/ simh] emulates the PDP-11 & a kind of more architectures, & includes software package kits for native operating systems (including RT-11).

PDP-11 models
A PDP-11 processors tended to fall into many natural groups dependent on the original project upon which it is depending & which I/O bus it utilized. inside both class action, virtually all system were offered in both versions, a single arranged for OEMs and one arranged for prevent-users. Unibus models
A charted system utilized a Unibus as their principal bus: PDP-11 (late renamed a PDP-11/20) and PDP-11/15 -- The original, direct execution processor. PDP-11/35 and 11/40 -- A microprogrammed successor to the /20. PDP-11/45, 11/50, and 11/55 -- A very much sooner microprogrammed processor even that can apply semiconductor memory also when or additionally to core memory. PDP-11/70 -- The 11/45 architecture expanded to allow 4 MB of physical memory segregated onto the personal memory bus, Two KB of cache memory, and lot sooner I/O gear attached via a Massbus. PDP-11/05 and 11/10 -- A numbers-reduced successor to the 11/20. PDP-11/34 and 11/04 -- Cost-reduced watch-in products to the 11/35 & 11/05. A PDP-11/09 & 11/39 exemplary list were documented internally to DEC however never produced purchasable. PDP-11/44 -- An extension of a 11/34 that included the cache memory and floating point units as a standard feature. This machine too involved the sophisticated serial console & trend lines for Little joe MB of physical memory unintegrated onto its have personal bus. PDP-11/60 -- A PDP-11 with user-writable microcontrol store.

Q-bus models
A resulting system utilized a Q-Bus as their principal bus: PDP-11/03 (also referred to as a LSI-11/03) -- A number 1 LSI PDP-11, this system utilized the chipset from either Western Digital.

PDP-11/23 -- 2nd generation of LSI (F-11)

PDP-11/73 -- a third generation LSI PDP, this system utilized the "Jaws-11" chip placed.

PDP-11/53 -- downsized 11/73

PDP-11/83 -- upsized 11/73 with PMI (personal memory interconnect)

Models that were available for either bus
PDP-11/23 & 11/24 -- A 2nd, great deal sooner LSI PDP-11, it used a "Fonz-11" chipset. This technique supported QuaternityMB of physical memory and a Commercial Instruction Placed. PDP-11/83 and 11/84 -- Another J-11 implementation.

Models without standard bus
PRO-300 PRO-350 PRO-380

These were desktop PCs designed to compete by having IBM's earliest 8088 & 80286 depending microcomputer. A system were equipped by having Quintet 1/4" floppy disk drives and hard disks. The CPUs were from the LSI-11 line running P/OS, which was essentially RSX-11M+. As the design was intended to avoid software exchange with existing PDP-11 models, their ill fate in the market was no surprise for anyone except DEC.

Models that were planned but never introduced
PDP-11/27 -- A Jaws-11 implementation that would have used the VAXBI Bus as its principal I/O bus.

PDP-11/74 -- A PDP-11/70 that was extended to contain multiprocessing features. Up to four processors could be interconnected, although the physical cable management became unwieldy. Another variation on the 11/74 contained both the multiprocessing features and the Commercial Instruction Set. A substantial number of prototype 11/74's (of various types) were built and at least two multiprocessor systems were sent to customers for beta testing, but no systems were ever officially sold. A four processor system was maintained by the RSX-11 operating system development team for testing and a uniprocessor system served PDP-11 engineering for general purpose timesharing.

PDP-11/68 -- A follow-on to the PDP-11/60 that would have supported 4MB of physical memory.

Special purpose versions
GT40 -- Vector graphic terminal built from a PDP11-05 GT44 -- Vector graphic terminal built from a PDP11-40 H-11 -- Heathkit OEM version of the LSI-11/03 VT103 -- VT100 with backplane to host a LSI-11 MINC-11 -- Laboratory system based on 11/03 or 11/23. C.mmp -- Multiprocessor system from Carnegie_Mellon_University.

Clandestine clones
The PDP-11 was sufficiently popular that several unauthorized clones were produced behind the Iron curtain. At least some of these were pin-compatible with DEC's PDP-11s and could share peripherals and system software. These include: SM-4, SM-1420, SM-1600, Electronics BK-0010, DVK, UKNC (in the Soviet Union) SM-4, SM-1420, IZOT-1016 and peripherials (in Bulgaria). SM-1420 (in East Germany) Mera (in Poland) SM-4 (in Hungary) Independent (in Romania)

Operating Systems
Several operating systems were available for the PDP-11

From Digital: DOS/BATCH IAS P/OS RSX-11 RT-11 RSTS/E Ultrix-11

From third parties: ANDOS MKDOS CSIDOS TRIPOS MUMPS Unix (many versions, including Version 7 Unix and 2BSD) TSX-Plus